Integrated circuit, communication unit and method for improved amplitude resolution of an RF-DAC

ABSTRACT

An integrated circuit comprises a digitally-controlled power generation stage (DPA) for converting an input signal to a radio frequency (RF) carrier, the DPA comprising a plurality of selectable switching devices capable of adjusting an envelope of the RF carrier; and a pulse width modulator (PWM) generator arranged to generate a PWM control signal and operably coupleable to the plurality of selectable switching devices of the DPA. The PWM generator inputs the PWM control signal to a subset of the plurality of the selectable switching devices such that a PWM signal adjusts the envelope RF carrier output from the DPA.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. provisional application No.61/329,159 (filed on Apr. 29, 2010) and U.S. provisional application No.61/407,186 (filed on Oct. 27, 2010). The entire contents of theserelated applications are incorporated herein by reference.

DESCRIPTION

1. Field of the Invention

The field of this invention relates to radio-frequencydigital-to-amplitude converter(s) (RF-DAC(s). The invention isapplicable to, but not limited to, radio-frequency digital-to-amplitudeconverter(s) (RF-DAC(s)) employing pulse width modulation.

2. Background of the Invention

One of the most important radio frequency (RF) architectural/circuitchanges in the last decade has been the digitization of RF transceivers,such that digital functionality in the RF domain is now a key aspect formost wireless applications. Thus, for low-cost and low-power wirelessdevices, system-on-chip (SoC) integration of RF circuits with digitalcircuits has proven to be popular. One example of this is in digital RFtransmitters, which now comprise digital application specific integratedcircuit (ASIC) cells and one or more radio-frequencydigital-to-amplitude converter(s) (RF-DAC(s)).

Some recent publications on RF transmitters have shown that employing anRF-DAC can make RF SoC implementation easier, for example R. Staszewski,et al. “All-digital PLL and transmitter for mobile phones”, published inIEEE J. Solid-State Circuits, vol. 40, no. 12, pp 2469-2482, December2005 [1], J. Mehta, et al. “A 0.8 mm2 II-digital SAW-less polartransmitter in 65 nm EDGE SoC”, published in Proc. of IEEE Solid-StateCircuits Conf, pp 58-59, December 2010 [2], A. Jerng, et al. “A widebandsigma-delta digital RF modulator for high data rate transmitters”,published in IEEE Solid-State Circuits, vol. 42, no. 8, pp 1710-1722,August 2007 [3], P. Eloranta, et al. “A multimode Transmitter in 0.13 μmUsing Direct-Digital RF Modulator”, published in IEEE J. Solid-StateCircuits, vol. 42, no. 12, pp 2774-2784, December 2007 [1]. Among them,the commercial single-chip GSM/EDGE transceiver in [1, 2] is unique inthat it uses a simple array of unit-weighted transistor switches tocontrol the output RF amplitude, which operates as near class-E poweramplifier, instead of using a traditional current-source based DACstructure.

Concurrently to the digitization of RF transceivers, the RF performancerequirements in wireless applications have been increasing, for exampleto support surface acoustic wave (SAW) filter removal, multi-modeoperation, multi-band operation, to meet coexistence requirements, etc.It is known that RF-DAC's need to achieve extremely-high resolutionperformance levels, which have so far been difficult to achieve in apractical, cost-effective manner. The traditional means of amplituderesolution in RF-DACs is limited due to device mismatches, where thetypical method of ΣΔ dithering through noise shaping does not work wellin SAW-less and multi-radio systems.

FIG. 1 illustrates the polar transmitter 100 introduced in [1, 2]. TheI/Q baseband data is converted into digital amplitude modulation (AM)and phase/frequency modulation (PM/FM) signals. The frequency signal isfed into the DCO-based N_(F)-bit digital-to-frequency converter (DFC),which generates a digital phase-modulated RF carrier by means of anall-digital PLL (ADPLL). The amplitude signal drives the N_(A)-bitdigital-to-RF-amplitude converter (DRAC), which includes adigitally-controlled power amplifier (DPA).

The DPA controls the envelope of the phase-modulated RF carrier, henceit is considered an RF-DAC. The DPA is different from the traditionalRF-DACs in [3] or [4], because it does not use current sources.Therefore, the DPA is more compatible with low-voltage and low-costdigital CMOS processes than the traditional RF-DAC. Lack of currentsources in the DPA results in somewhat compressed transfer function, butthe look-up-table (LUT) for AM-AM and AM-PM predistortion in theamplitude signal path shown in FIG. 1 linearizes the DPA transferfunction.

Referring now to FIG. 1, a known polar transmitter based on a DCO andDPA circuits from [2] is illustrated. For simplicity purposes, theall-digital PLL around the DCO is not shown. References [1, 2] haveproved that the architecture in FIG. 1 is feasible for SoC meeting allGSM and EDGE specifications. However, the resolution of the amplitudemodulation path is limited by lithography and RF mismatches (i.e., bothamplitude and phase/delay) of the unit switching devices in the DPA,and, consequently, the polar transmitter has little margin in thefar-out (i.e., the associated RX band) noise limit of the SAW-lessoperation for EDGE.

The amplitude resolution could be improved by ΣΔ dithering of the unittransistor switches [1, 2]. However, the quantization noise is pushed tohigher frequencies where emission requirements might sometimes bedifficult to satisfy, especially when considering radio coexistence in awireless connectivity (e.g., Bluetooth, WLAN) or in a multi-core RF-SoCenvironment.

Referring now to FIG. 2, a known concept 200 of achieving amplitudemodulation (AM) through pulse width modulation (PWM) is illustrated. Asshown, in the graphical waveform, the RF output amplitude is“proportional” to the duty cycle of a power amplifier input (PA_IN)signal. A duty cycle of the AM signal is controlled through precisedelay.

The output amplitude of a PWM signal at the frequency of interest,however, is incorrect if the pulsewidth is chosen in a straightforwardway, such that the DC amplitude of the PWM signal is correct, asillustrated in S. E. Meninger and M. H. Perrott, titled “A fractional-Nsynthesizer architecture utilising a mismatch compensated PFD/DACstructure for reduced quantization-induced phase noise” published inIEEE Trans. Circuits Systems, vol. 50, issue 11, pp. 839-849, November2003 [7], which is incorporated herein by reference and S. E. Meningerand M. H. Perrott, titled “An RF Pulse Width Modulator for switch modepower amplification of varying envelope signals” published in Proc.Silicon Monolithic Integrated Circuits in RF System Top meeting, pp.277-280, January 2007 [8], which is incorporated herein by reference.This is in contrast with the normal up-conversion operation of the DPA,which acts as a mixer. As a result, this inaccurate RF output level atthe carrier frequency turns out to limit the resolution improvement.

Thus, a need exists for an improved amplitude resolution of an RF-DACand method therefor.

SUMMARY OF THE INVENTION

Accordingly, the invention seeks to mitigate, alleviate or eliminate oneor more of the above mentioned disadvantages singly or in anycombination. Aspects of the invention provide an integrated circuitcontroller, method of controlling an output of a digitally-controlledpower amplifier (DPA), and a wireless communication unit as described inthe appended claims. These and other aspects of the invention will beapparent from, and elucidated with reference to, the embodimentsdescribed hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

Further details, aspects and embodiments of the invention will bedescribed, by way of example only, with reference to the drawings.Elements in the figures are illustrated for simplicity and clarity andhave not necessarily been drawn to scale. Like reference numerals havebeen included in the respective drawings to ease understanding.

FIG. 1 illustrates a known polar transmitter based on a DCO and DPAcircuits from [2].

FIG. 2 illustrates a known concept of achieving amplitude modulationthrough pulse width modulation.

FIG. 3 illustrates an example of amplitude resolution improvementmechanism by incrementally adding a PWM driven transistor.

FIG. 4 illustrates an amplitude resolution improvement mechanism byfirst (a) horizontal slicing, (b) vertical slicing with centered PWM,(c) vertical slicing with non-centered PWM and secondly by (d) thefractional portion of horizontal slicing, (e) the fractional portion ofvertical slicing with centered PWM, (f) the fractional portion ofvertical slicing with non-centered PWM.

FIG. 5 illustrates a graphical example of frequency domainamplitude/phase comparison of horizontal slicing and vertical slicing(centered PWM and non-centered PWM) when v=⅜ and

$T = {\frac{3}{8} \times {\frac{T}{2}.}}$

FIG. 6 illustrates a graphical example of amplitude quantization step atthe carrier frequency of horizontal slicing signals and 8-level PWMsignals from [8].

FIG. 7 illustrates a graphical example of symbol trajectories for anEDGE signal in I/Q plane, with (a) ideal trajectory (b) quantizedtrajectory without amplitude or phase error (c) quantized trajectorywith phase error.

FIG. 8 illustrates a graphical example of frequency domain amplitudecomparison of horizontal slicing and centered PWM when v=⅜ andτ=0.122×T.

FIG. 9 illustrates a graphical example of (a) Vectors of an integer partof the amplitude signal and a horizontal slicing's fractional part (b)an integer part and a centered PWM's fractional part (c) an integer partand a non-centered PWM's fractional part.

FIG. 10 illustrates a graphical example of (a) Horizontal slicing (b)non-centered PWM in complex plane, where the entire complex plane isrotated 90° counter-clockwise.

FIG. 11 illustrates a graphical example of a phase compensationcomparison between equation (11) and equation (13) given below.

FIG. 12 illustrates a graphical example of timing diagrams of phasecompensation for non-centered PWM.

FIG. 13 illustrates an example of a polar transmitter with centered PWMin accordance with some example embodiments of the invention.

FIG. 14 illustrates an example of a conceptual block diagram of acentered PWM generator and its timing diagram, in accordance with someexample embodiments of the invention.

FIG. 15 illustrates an example of a polar transmitter with non-centeredPWM, in accordance with some example embodiments of the invention.

FIG. 16 illustrates an example of a conceptual block diagram of anon-centered PWM generator and its timing diagram, in accordance withsome example embodiments of the invention.

FIG. 17 illustrates an example of a conceptual delay chain for a PWMgenerator, in accordance with some example embodiments of the invention.

FIG. 18 illustrates an example of a 4-inverter delay circuit, inaccordance with some example embodiments of the invention.

FIG. 19 illustrates an example of a 3-inverter delay circuit, inaccordance with some example embodiments of the invention.

FIG. 20 illustrates an example of delay-chain circuits including controllogic, in accordance with some example embodiments of the invention.

FIG. 21 illustrates a graphical example of a mismatch-averagedpropagation (mean) delay versus input code of the circuit of FIG. 20, inaccordance with some example embodiments of the invention.

FIG. 22 illustrates an example of mean delays and standard deviations ofthe inverter stage of FIG. 20, in accordance with some exampleembodiments of the invention.

FIG. 23 illustrates an example of a mean delay of each inverter stage ofthe circuit of FIG. 20, in accordance with some example embodiments ofthe invention.

FIG. 24 illustrates a graphical example of a resolution comparison ofcentered and non-centered PWM generators with a unit delay of

$\frac{1}{8} \times \frac{T}{2}$(a) centered PWM (b) non-centered PWM, in accordance with some exampleembodiments of the invention.

FIG. 25 illustrates an example of an output spectrum of a 10-bit DPA anda DPA with 12-level centered PWM signals with/without the amplitudepredistortion LUT, in accordance with some example embodiments of theinvention.

FIG. 26 illustrates an example of an output spectrum of a 10-bit DPA anda DPA with 12-level centered PWM signals with/without delay mismatch, inaccordance with some example embodiments of the invention.

FIG. 27 illustrates an example of an output spectrum of a centered PWMwithout position offset vs. centered PWM with 18-psec. position offset,where delay mismatch is not considered, in accordance with some exampleembodiments of the invention.

FIG. 28 illustrates an example of an output spectrum of a 10-bit DPA anda DPA employing non-centered PWM signals with/without phasecompensation, in accordance with some example embodiments of theinvention.

FIG. 29 illustrates an example of an output spectrum of a DPA employingnon-centered PWM signals with reduced size of an amplitude predistortionLUT by approximation, in accordance with some example embodiments of theinvention.

FIG. 30 illustrates an example of an output spectrum of a DPA employingnon-centered PWM signals with reduced size of a phase predistortion LUTby approximation, in accordance with some example embodiments of theinvention.

FIG. 31 illustrates an example of an output spectrum of a DPA employingnon-centered PWM signals with different resolutions of a phase path, inaccordance with some example embodiments of the invention.

FIG. 32 illustrates an example of an output spectrum of a DPA employingnon-centered PWM signals with delay mismatch, in accordance with someexample embodiments of the invention.

FIG. 33 illustrates an example of a wireless communication unit adaptedto employ example embodiments of the invention.

FIG. 34 illustrates an example of a RF-DAC employing PWM according toexample embodiments of the invention.

FIG. 35 illustrates timing waveforms of the example RF-DAC employing PWMof FIG. 34 according to example embodiments of the invention.

FIG. 36 illustrates an example of a delay cell design, adapted to employexample embodiments of the invention.

FIG. 37 illustrates a first bit-quantization example of the exampleRF-DAC employing PWM of FIG. 34 according to example embodiments of theinvention.

FIG. 38 illustrates graphically a comparison of the two quantizationmethods to achieve the 3-bit quantization in the bit-quantizationexample employing PWM of FIG. 34 and FIG. 37 according to exampleembodiments of the invention.

FIG. 39 graphically a bit-quantization example using digitalpre-distortion for a PWM pulse width of FIG. 34 according to exampleembodiments of the invention.

FIG. 40 illustrates a flowchart of an operation of a RF-DAC employingiPWM according to example embodiments of the invention.

DETAILED DESCRIPTION

Examples of the invention will be described in terms of an integratedcircuit (IC) comprising a radio-frequency digital-to-amplitude converter(RF-DAC) employing pulse width modulation (PWM). In examples of theinvention, PWM is applied in an incremental fashion. Thus, hereinafterthe term incremental PWM (iPWM) may be used to encompass and adjustmentto (e.g. increment or decrement) a PWM signal. An RF-DAC is based on aconcept of a digitally-controlled power amplifier (DPA). In general, aRF-DAC comprises a number of components, one of which is a powergeneration stage. Hereinafter, such a power generation stage will bedescribed in the context of a DPA, as this term is widely used in theliterature. Notwithstanding the above, in some instances, as these twoterms RF-DAC and DPA are closely related, inasmuch as the DPA in someexamples may equate to the RF-DAC with other components being providedexternal to an RF-DAC IC, the two terms may be used henceforthinterchangeably. For completeness, it is noted that the term ‘DPA’ issomewhat of a misnomer, since the DPA input is not an analog RF signaland thus the notion of a ‘gain’ is incorrect here. Notwithstanding theaforementioned clarification of terms, it will be appreciated by askilled artisan that the inventive concept herein described may beembodied in any type of RF-DAC design.

Example embodiments of the invention focus on time-domain resolution ofa digital signal edge transition, rather than the typical voltageresolution of analog signals, to improve the resolution of RF-DACperformance. Such an approach is particularly beneficial when using ahighly-scaled CMOS technology. Examples of the invention will also bedescribed in terms of a digitally controlled power amplifier (DPA) thatis used as an RF-DAC and arranged to convert a digital word intoamplitude of an RF carrier. In this manner, examples of the inventionmay benefit from surface acoustic wave (SAW)-less implementations (e.g.designs without a requirement of a transmit bandpass filter connected tothe RF output pin). Examples of the invention will also be described interms of ‘EDGE’ (sometimes referred to as 2.5G) operation, standardisedby the third generation partnership project (3GPP™), which requires 13bits of amplitude modulation (AM) resolution for flat Q-noise to meetthe EDGE wideband noise specification. Using the known technique ofapplying voltage resolution of analog signals to improve the resolutionof RF-DAC performance has been found to be difficult to achieve an AMresolution of >10 bits by means of device matching alone.

Example embodiments of the invention are described to help mitigate thefar-out noise issue and make the digitally-intensive polar architectureof FIG. 1 more attractive to multi-core RF integration, as well as tomeet advanced modulation standards. Example embodiments of the inventionpropose an RF-DAC structure in which significant resolution improvementis achieved by means of incremental pulse width modulation (PWM). PWM isa time-domain operation since the signal is carried in width or durationof a pulse, which is time-domain information. In modern CMOS technology,time-domain processing can achieve higher resolution thanvoltage/current-domain processing because the switching time improves bydevice scaling, as described in R. B. Staszewski's Ph.D. thesis fromUniv. of Texas, Dallas, USA “Digital deep-submicron CMOS frequencysynthesis for RF wireless applications” [5], which is incorporatedherein by reference. Although the novel and inventive amplituderesolution improvement is verified with a digital polar transmitter, inexample embodiments of the invention, it may be also applied todigitally-intensive I/Q architecture.

In example embodiments of the invention, the PWM may be categorized intocentered PWM and non-centered PWM depending on the relative pulseposition. The amplitude resolution improvement with centered PWM ispresented in [6], which is incorporated herein by reference. Exampleembodiments of the invention may extend the PWM scheme with non-centeredPWM, and compare it with the centered PWM scheme in the context ofimplementation and performance.

Example embodiments of the invention discuss the details of the PWMscheme to improve the amplitude resolution of the DPA. It will be shownthat both centered and non-centered PWM create an incorrect RF signalwhen the pulse width is chosen in a straightforward way. Predistortionof PWM signals to generate a correct RF signal is then presented. LUTsize reduction technique for the non-centered PWM scheme will thenfollow. Different polar transmitter architectures for centered PWM andnon-centered PWM are described, and behavioural simulation results ofeach PWM scheme are presented to show the benefits of the describedmethods.

Example embodiments of the invention describe a DPA that is augmented byat least one additional unit switching device that is driven by a PWMcontrol signal, such that a PWM generator inputs the PWM control signalto a subset of a plurality of selectable switching devices such that aPWM signal adjusts the envelope RF carrier output from the DPA, as shownin FIG. 3. In this context, the term ‘adjusts’ encompasses adding,subtracting, combining, incrementing, decrementing or any other mannerto modify the envelope RF carrier output from the DPA with a PWM controlsignal. However, in some examples, the amplitude resolution of the DPAimproves by turning on the added switching device for only a short timeinterval, for example within the positive half-cycle of the RF period.The RF output amplitude will be controlled by the time interval, and theresolution may be determined by the time precision of the turning-onsignal.

Referring now to FIG. 3, an amplitude resolution improvement circuit300, adding a PWM driven transistor, is illustrated. The amplituderesolution of the DPA in FIG. 3 is now limited by the time resolution ofthe PWM. In modern CMOS processes, the switching time gets typicallyimproved by 0.7× per technology scaling node; hence, achieving higherresolution in the time-domain is easier than in thevoltage/current-domain. In a 65 nm CMOS process, a minimum timeresolution of 20 psec is easy to guarantee over process, temperature,and voltage variations.

The switching devices in the original system are controlled by aninteger word of the digital amplitude signal. In order to increase theamplitude resolution of the original DPA, a fractional word of theamplitude controls the extra switching device in FIG. 3. Thus, themaximum error that the additional device can cause is less than thequantization noise of the original system. As a result, the added noiseor jitter on the PWM signal does not affect the overall performance.

Referring now to FIG. 4, a graphical example of amplitude resolutionimprovement by (a) horizontal slicing, (b) vertical slicing withcentered PWM, (c) vertical slicing with non-centered PWM is illustrated.To explain this issue, FIG. 4 first illustrates three differentquantization methods 400 for adding an extra 3-bit resolution in eithera voltage or current signal. For the DPA, the vertical axis in FIG. 4represents the current or the conductance of the switching transistors,which is directly proportional to the output envelope, and its originalresolution is 10 bits in the system of FIG. 1. FIG. 4-(a) showshorizontal slicing of a signal, which is a conventional quantizationmethod for a DAC. Both FIG. 4-(b) and FIG. 4-(c) show vertical slicingof a signal where the output amplitude is controlled by the timeinterval of the vertically sliced signal. Note that the pulse in FIG.4-(b) is located at the center, whereas that in FIG. 4-(c) is aligned att=0. This quantization method is PWM whose pulsewidth has a limitednumber of quantized pulsewidths. Depending on the position of theadditive pulse, the vertical slicing method could be categorized ascentered PWM and non-centered PWM, as shown in FIG. 4-(b) and FIG.4-(c).

For the horizontal slicing scheme, the resolution is set by availablearea and power of switching transistors along with device mismatch,which limits the minimum device size. In contrast, the resolution of thevertical slicing scheme is set by the time-resolution. Accordingly, thevertical slicing can achieve higher resolution than the horizontalslicing with the same minimum device size if the time-resolution isfiner. In modern nanometer-scale CMOS technology, the time-resolution isgetting better, thus employing PWM seems a better choice to improve theamplitude resolution of a DPA.

Referring now to the second portion 450 of FIG. 4, an amplituderesolution improvement mechanism by (d) the fractional portion ofhorizontal slicing, (e) the fractional portion of vertical slicing withcentered PWM, (f) the fractional portion of vertical slicing withnon-centered PWM is illustrated. The second portion 450 of FIG. 4illustrates only the first fractional portions from FIG. 4, where T isthe time period of an RF carrier signal, v is an voltage/current levelgenerated by the unit switching device using horizontal slicing, and τis a pulsewidth for vertical slicing. Note that the amplitude switchesare only turned on during half the DCO period

$,{\frac{T}{2}.}$The full size of the voltage/current level generated by the unitswitching device is normalized to ‘1’. In this example, the fractionalword adds an extra 3-bit resolution with 8 extra amplitude levels. Thepulse position of the PWM signal could be at the center of the firsthalf cycle of the carrier signal (centered PWM), or it could be alignedwith the main switching waveform (non-centered PWM).

Intuitively, all the signals from FIG. 4-(d), (e), (f) are the same interms of power because the total area of the signals are the same.However, as pointed out in [7], which is incorporated herein byreference, they are equivalent only at DC. The Fourier transforms of thehorizontal and vertical slicing signals are

${X_{H}({j\omega})} = {{\int_{0}^{\frac{T}{2}}{{v \cdot {\mathbb{e}}^{{- {j\omega}}\; t}}{\mathbb{d}t}}} = {v \cdot \frac{2{{\mathbb{e}}^{{- j}\frac{\omega\; T}{4}} \cdot {\sin\left( \frac{\omega\; T}{4} \right)}}}{\omega}}}$${X_{C}({j\omega})} = {{\int_{\frac{T}{4} - \frac{T}{2}}^{\frac{T}{4} + \frac{T}{2}}{{\mathbb{e}}^{{- {j\omega}}\; t}{\mathbb{d}t}}} = \frac{2{{\mathbb{e}}^{{- j}\frac{\omega\; T}{4}} \cdot {\sin\left( \frac{\omega\; T}{2} \right)}}}{\omega}}$${X_{NC}({j\omega})} = {{\int_{0}^{T}{{1 \cdot {\mathbb{e}}^{{- {j\omega}}\; t}}{\mathbb{d}t}}} = \frac{2{\mathbb{e}}^{{- j}\frac{\omega\; T}{2}}{\sin\left( \frac{\omega\; T}{2} \right)}}{\omega}}$where X_(H)(jω), X_(C)(jω), and X_(NC)(jω) are the Fourier transforms ofthe horizontal slicing, the centered PWM, and the non-centered PWMsignals, respectively. In the examples of FIG. 4, v is ⅜, and τ is

$\frac{3}{8} \times {\frac{T}{2}.}$

FIG. 5 illustrates the amplitudes and the phases of the Fouriertransforms of each case, and it clearly shows that horizontal andvertical slicing is not the same at the carrier frequency, which is

$\frac{1}{T}{{Hz}.}$First of all, the amplitude of the Fourier transform of horizontalslicing is different from that of vertical slicing. Second of all, thephase of vertical slicing with non-centered PWM is different from thatof horizontal slicing although the phase of centered PWM is the same asthat of horizontal slicing. An RF-DAC is intended to generate a signalat a carrier frequency corresponding to an input digital code.Therefore, the vertical slicing signal in FIG. 5 creates an incorrect RFsignal even though it creates an accurate DC signal.

An inaccurate RF signal from an RF-DAC leads to higher quantizationnoise. The Fourier transforms at a carrier frequency

$\left( {\omega = \frac{2\pi}{T}} \right)$should be examined for quantization noise analysis for an RF-DAC, andthey are

$\begin{matrix}{{{X_{H}({j\omega})}❘_{\omega = \frac{2\pi}{R}}} = \frac{{- j}\;{vT}}{\pi}} & (1) \\{{{X_{C}({j\omega})}❘_{\omega = \frac{2\pi}{T}}} = \frac{{- {{jsin}\left( \frac{\pi\; T}{T} \right)}}T}{\pi}} & (2) \\{{{X_{NC}({j\omega})}❘_{\omega = \frac{2\pi}{T}}} = {\left( {{\mathbb{e}}^{{- {j{({\pi\;{T/T}})}}}*}{\sin\left( {\omega\;{T/2}} \right)}^{*}T} \right)/\pi}} & (3)\end{matrix}$

FIG. 6 depicts the amplitudes at the carrier frequency of the 8-levelhorizontal and vertical slicing signals, which are derived in (1) and(2) as a function of pulsewidth and horizontal slicing level. Note thatthe amplitudes of (2) and (3) are the same. The maximum amplitude at thecarrier frequency is normalized to 1 for simple quantization errorestimation, and Table I shows the RF amplitude for each input code andthe corresponding quantization error. In Table I, the range of thequantization error of vertical slicing is much larger than 1/16=0.0625.It means that the quantization noise by vertical slicing is bigger thanthat of horizontal slicing. The quantization noise power can beestimated by a probability density function assuming the probability oferror is uniformly distributed. The calculated noise power shows thathorizontal slicing achieves 3-bit resolution while vertical slicingachieves only 0.9-bit resolution. Therefore, resolution improvement byPWM is severely impaired if the pulsewidth is chosen in such a way thatthe DC amplitude of a vertical slicing signal is matched with that of ahorizontal slicing signal, as shown in FIG. 6 and Table I.

TABLE 1 Quantization error by horizontal and centered PWM horizontalslicing centered PWM original pulse amp quantization amp quantizationinput width at f_(C) error at f_(C) error   0-1/16 0 0 −1/16-0     0−1/16-0     1/16-3/16 $\frac{1}{8} \cdot \frac{T}{2}$ ⅛ −1/16-1/16  0.194 0.132-0.007 3/16-5/16 $\frac{2}{8} \cdot \frac{T}{2}$ 2/8−1/16-1/16   0.383 0.195-0.070 5/16-7/16 $\frac{3}{8} \cdot \frac{T}{2}$⅜ −1/16-1/16   0.556 0.243-0.118 7/16-9/16$\frac{4}{8} \cdot \frac{T}{2}$ 4/8 −1/16-1/16   0.707 0.270-0.145 9/16-11/16 $\frac{5}{8} \cdot \frac{T}{2}$ ⅝ −1/16-1/16   0.8320.269-0.144 11/16-13/16 $\frac{6}{8} \cdot \frac{T}{2}$ 6/8 −1/16-1/16  0.924 0.236-0.111 13/16-15/16 $\frac{7}{8} \cdot \frac{T}{2}$ ⅞−1/16-1/16   0.981 0.168-0.043 15/16-16/16$\frac{8}{8} \cdot \frac{T}{2}$ 8/8 −1/16-0     1 −1/16-0  Vertical slicing with non-centered PWM distorts the signal even furtherdue to it phase discrepancy. The phase of the Fourier transforms in

${(1)\mspace{14mu}{and}\mspace{14mu}(2)\mspace{14mu}{is}} - \frac{\pi}{2}$regardless of v or τ, but the phase in (3) is dependent on τ.Accordingly, the phase of the Fourier transforms of the horizontalslicing signals and the non-centered PWM signals are different unless

$T\mspace{14mu}{is}\mspace{14mu}{\frac{T}{2}.}$Thus, the phase of non-centered PWM should be compensated for thecorrect symbol representation.

The importance of phase compensation is presented in FIG. 7. Itillustrates the trajectories of an example of EDGE symbols in an I/Qplane with and without phase error. FIG. 7-(a) shows the ideal symboltrajectory without any amplitude/phase quantization. FIG. 7-(b) showsthe symbol trajectory with amplitude quantization. There is no phaseerror in this case so that its spectrum will show only the noise due tothe amplitude quantization error. Horizontal slicing and centered PWMsignals will show this symbol trajectory. FIG. 7-(c) shows thetrajectory with amplitude quantization and phase error. Even though ithas the same amplitude quantization as 7-(b), the phase error results inuneven symbol trajectory, which will cause more noise in the spectrum.

Predistortion of PWM Signals

Amplitude distortion of PWM exists for both centered and non-centeredPWM. In contrast, phase distortion is caused by only non-centered PWM.We will first discuss how to avoid or reduce amplitude distortion ofcentered PWM, which was briefly introduced in [6], and then discussphase and amplitude distortion of non-centered PWM.

Predistortion of PWM Signal for Centered PWM

One solution to the amplitude discrepancy between horizontal slicing andcentered PWM is choosing the pulsewidth for the vertical slicing suchthat its amplitude at the carrier frequency is the same as that ofcorresponding horizontal slicing.

$\begin{matrix}{{{{X_{H}({j\omega})}❘_{\omega = \frac{2\pi}{T}}} = {{{X_{C}({j\omega})}❘_{\omega = \frac{2\pi}{T}}\frac{{- j}\;{vT}}{\pi}} = \frac{{- j}\;{\sin\left( \frac{\pi\; T}{T} \right)}T}{\pi}}}{v = {\sin\left( \frac{\pi\; T}{T} \right)}}} & (4)\end{matrix}$Equation (4) shows how to choose the pulsewidth for the centered PWMsignal. A centered PWM signal whose pulsewidth satisfies (4) has thesame amplitude as the corresponding horizontal slicing signal at thecarrier frequency. Note that the centered PWM signal has the same phaseas that of the horizontal slicing signal. Thus, phase distortion is nota concern for a centered PWM signal.

TABLE 2 Pulsewidths that create the same amplitude at a carrierfrequency as the corresponding horizontal slicing signals horizontalslicing pulsewidth 0 0 ⅛ 0.0399 × T  2/8 0.0804 × T  ⅜ 0.122 × T 4/80.167 × T ⅝ 0.215 × T 6/8 0.270 × T ⅞ 0.339 × TFIG. 8 depicts an example of the amplitude of the Fourier transform ofthe centered PWM signal satisfying (4). In FIG. 8, it is clear that theamplitude of the centered PWM signal at the carrier frequency is thesame as that of the horizontal slicing signal. Table 2 shows an exampleof the pulsewidths, for which the amplitude and the phase at the carrierfrequency is the same as those of the corresponding horizontal slicingsignals. The amplitude resolution of the centered PWM signals employingthe pulsewidths shown in Table 2 is also the same as that of horizontalslicing signals. Unfortunately, the pulsewidths shown in Table 2 arevery challenging to generate without an accurate delay controller, suchas a high precision DLL or a fine-resolution delay line. Therefore, suchPWM generation is impractical.

TABLE 3${Pulsewidths},{{which}\mspace{14mu}{are}\mspace{14mu}{the}\mspace{14mu}{multiples}\mspace{14mu}{of}\mspace{14mu}\frac{T}{16}},$and the equivalent horizontal slicing signals horizontal horizontalslicing pulsewidth slicing pulsewidth 0 0 0.707$\frac{4}{8} \times \frac{T}{2}$ 0.194 $\frac{1}{8} \times \frac{T}{2}$0.831 $\frac{5}{8} \times \frac{T}{2}$ 0.383$\frac{2}{8} \times \frac{T}{2}$ 0.924 $\frac{6}{8} \times \frac{T}{2}$0.556 $\frac{3}{8} \times \frac{T}{2}$ 0.981$\frac{7}{8} \times \frac{T}{2}$A PWM signal is easier to generate when its pulsewidth is integermultiples of a certain stable delay. Table 3 shows an example in whichthe pulsewidths are integer multiples of

$\frac{T}{16}.$It also presents the corresponding horizontal slicing signals thatsatisfy (4). A simple delay chain can generate those pulsewidths shownin Table 3; hence, it is a better implementation choice. However, therelationship between the desired horizontal slicing signals and thepulsewidths shown in Table 3 is nonlinear. A predistortion digital LUTcan be utilized to implement this mapping, where the contents of thepredistortion LUT should be chosen such that the amplitude quantizationerror is minimized.

Table 4 presents an example of a predistortion digital LUT for mappingthe input code to the appropriate pulsewidth of centered PWM. In theexample of Table 4, the LUT maps the 5-bit input to 8-level pulsewidths.The LUT mapping linearizes the relationship between the input code andthe output amplitude at the carrier frequency such that the amplitudequantization error is minimized. Note that the range of the quantizationerrors in Table 4 are sometimes larger than the maximum quantizationerror of the ideal 8-level signal, which is ± 1/16=±0.0625. FIG. 6explains the reason of the larger quantization noise of the LUT in Table4 more clearly. The quantization step is larger than that of ideal8-level horizontal slicing when the pulsewidths are relatively short, asshown in FIG. 6. Therefore, the quantization error using thepredistortion LUT and 8-level centered PWM will be larger than that ofthe ideal 3-bit horizontal slicing. The quantization noise power of thecentered PWM employing the LUT in Table 4 can be also calculated byprobability density functions, and the calculated amplitude resolutionat the carrier frequency is 2.6 bits.

As we have seen in Table 2 and Table 3, there are two options tolinearize the RF power of a PWM signal: mapping uniform data input tonon-uniform pulsewidths (Table 2), and mapping non-uniform data input touniform pulsewidths (Table 3). Apparently, uniform-to-non-uniformmapping needs no sacrifice for achieving 3-bit resolution, whilenon-uniform-to-uniform mapping shows the resolution degradation by 0.4bits. However, the pulsewidths in Table 3 are easy to generate using asimple delay chain. The predistortion LUT is also easy to implement indigital CMOS processes. Therefore, we propose to employ a predistortionLUT for centered PWM, which helps to minimize the overall systemcomplexity with slight degradation of amplitude resolution.

TABLE 4 Look-up-table example with 5-bit input and 8-level centered PWMoutput original LUT pulsewidth amp quantization input input selected atf_(C) error   0-1/64 0 0 0    0-0.0156 1/64-3/64 1/32 0 0 0.0156-0.04693/64-5/64 2/32 0 0 0.0469-0.0781 5/64-7/64 3/32 0 0 0.0781-0.109 7/64-9/64 4/32 $\frac{1}{8} \cdot \frac{T}{2}$ 0.194 −0.0857-0.0545   9/64-11/64 5/32 $\frac{1}{8} \cdot \frac{T}{2}$ 0.194 −0.0545-0.0232  11/64-13/64 6/32 $\frac{1}{8} \cdot \frac{T}{2}$ 0.194 −0.0232-0.00804   13/64-15/64 7/32 $\frac{1}{8} \cdot \frac{T}{2}$0.194 0.00804-0.0393  15/64-17/64 8/32 $\frac{1}{8} \cdot \frac{T}{2}$0.194 0.0393-0.0705 17/64-19/64 9/32 $\frac{1}{8} \cdot \frac{T}{2}$0.194 0.0705-0.102  19/64-21/64 10/32 $\frac{2}{8} \cdot \frac{T}{2}$0.383 −0.0858-0.0546   21/64-23/64 11/32 $\frac{2}{8} \cdot \frac{T}{2}$0.383 −0.0546-0.0233   53/64-55/64 27/32 $\frac{5}{8} \cdot \frac{T}{2}$0.831 −0.00335-0.0279    55/64-57/64 28/32$\frac{5}{8} \cdot \frac{T}{2}$ 0.831 0.0279-0.0592 57/64-59/64 29/32$\frac{6}{8} \cdot \frac{T}{2}$ 0.924  −0.0333-0.00201   59/64-61/6430/32 $\frac{6}{8} \cdot \frac{T}{2}$ 0.924 −0.00201-0.0292   61/64-63/64 31/32 $\frac{7}{8} \cdot \frac{T}{2}$ 0.981 −0.0277-0.00359   63/64-64/64 31/32 $\frac{7}{8} \cdot \frac{T}{2}$0.981 −0.0156-0     Predistortion of PWM Signals for Non-Centered PWM

In contrast to the centered PWM, phase compensation is required fornon-centered PWM as the phase of the Fourier transforms of thehorizontal slicing signals and the non-centered PWM signals aredifferent. Therefore, the phase error created by a non-centered PWMsignal should be compensated. The novel and inventive PWM scheme isverified with a digital polar transmitter including a PLL, which canmanipulate the phase of an RF signal. The PLL can compensate the phaseerror, but it requires an additional LUT for the phase signal path.

Not only the phase but also the amplitude of the Fourier transform ofnon-centered PWM is different from that of centered PWM. Equations (1),(2), and (3) are the Fourier transforms of the fractional part of theamplitude signal only. The Fourier transforms of the complete signalsincluding both the integer and the fractional portions are:

$\begin{matrix}{{{X_{H,{total}}({j\omega})}❘_{\omega = \frac{2\pi}{T}}} = {\frac{{- j}\;{VT}}{\pi} + \frac{{- j}\;{vT}}{\pi}}} & (5) \\{{{X_{C,{total}}({j\omega})}❘_{\omega = \frac{2\pi}{T}}} = {\frac{{- j}\;{VT}}{\pi} + \frac{{- {{jsin}\left( \frac{\pi\; T}{T} \right)}}T}{\pi}}} & (6) \\{{{X_{{NC},{total}}({j\omega})}❘_{\omega = \frac{2\pi}{T}}} = {{{- j}\;{{VT}/\pi}} + {\left( {{\mathbb{e}}^{{- {j{({\pi\;{T/T}})}}}*}{\sin\left( {\pi\;{T/T}} \right)}^{*}T} \right)/\pi}}} & (7)\end{matrix}$where:

X_(H,total)(jω), X_(C,total)(jω), and X_(NC,total)(jω) are the Fouriertransforms of the horizontal slicing, the centered PWM, and thenon-centered PWM signals, respectively, including both the integer andfractional part. V is the integer portion, which is generated by a DPA.In some example embodiments, as described herein, the DPA may encompassa subset of the full DPA (e.g. a subset of the full power generationstage). The phases of the integer part and the fractional part inequations (5) and (6) are the same. Therefore, if the fractional portionof a centered PWM signal in equation (6) is the same as that of thetargeted horizontal slicing signal in equation (5), then the amplitudesof the complete signals are the same. In other words, τ for centered PWMis only dependent on v not V. However, as shown in equation (7), thephase of the fractional part of a non-centered PWM signal is differentfrom that of the integer part; hence, the amplitude of the final signalis a vector sum in complex plane. FIG. 9 illustrates the situation moreclearly. The goal of choosing the appropriate pulsewidth τ for centeredand non-centered PWM is to make the total signal including the integerportion the same as the ideal horizontal slicing signal, which isdepicted in FIG. 9-(a). For centered PWM, it is a simple task becausethe pulsewidth τ is determined by only v, and it is independent of theinteger portion V. For non-centered PWM, however, the phase of thefractional portion is not the same as that of the integer portion; as aresult, the amplitude of the total signal is a vector sum of the integerand the fractional parts, as shown in FIG. 9-(c). The vector sum is afunction of the integer part as well as the pulsewidth τ. Therefore, theamplitude predistortion LUT for non-centered PWM should take the integerpart into consideration while the LUT for centered PWM only takes thefractional part as its input. In other words, the size of the amplitudepredistortion LUT for non-centered PWM should be bigger than the LUT forcentered PWM.

As an example, the full-length size of the amplitude predistortion LUTfor the non-centered PWM should be 32768 words (15-bit=10-bit+5-bit) ifthe integer word of the amplitude is 10 bits and the fractional word is5 bits. However, the size of the amplitude predistortion LUT forcentered PWM will be only 32 words (5-bit) because the LUT takes onlythe fractional part as an input. Accordingly, non-centered PWM requiresmuch bigger amplitude predistortion LUT than centered PWM.

Nevertheless, under certain conditions, the size of the amplitudepredistortion LUT for non-centered PWM can be significantly reduced byapproximation. According to the equation below, the phase of the integerpart is always imaginary, and the phase of the fractional part has bothreal and imaginary parts that depend on τ. Note that the real part comesonly from the fractional word. The equation below can be separated intothe real and imaginary part, and the real part can be neglected if theinteger portion, V, is much larger than the fractional portion, asfollows.

$\begin{matrix}{{{\begin{matrix}{{{X_{{NC},{total}}({j\omega})}❘_{\omega = \frac{2\pi}{T}}} = {\frac{{- j}\;{VT}}{\pi} + \frac{{\mathbb{e}}^{{- j}\frac{\pi\; T}{T}}{\sin\left( \frac{\pi\; T}{T} \right)}T}{\pi}}} \\{= {\frac{{- j}\;{VT}}{\pi} - \frac{{{jsin}\left( \frac{\pi\; T}{T} \right)}{\sin\left( \frac{\pi\; T}{T} \right)}T}{\pi} +}} \\{\frac{{\cos\left( \frac{\pi\; T}{T} \right)}{\sin\left( \frac{\pi\; T}{T} \right)}T}{\pi}}\end{matrix}{{X_{{NC},{total}}({j\omega})}❘_{\omega = \frac{2\pi}{T}}{\approx {\frac{{- j}\;{VT}}{\pi}\frac{{jsin}\left( \frac{\pi\; T}{T} \right){\sin\left( \frac{\pi\; T}{T} \right)}T}{\pi}}}}{{if}\mspace{14mu} V}}\mspace{11mu} }\mspace{11mu}{\cos\left( \frac{\pi\; T}{T} \right)}{\sin\left( \frac{\pi\; T}{T} \right)}} & (8)\end{matrix}$Equation (8) is valid if V is large enough. In FIG. 10, we can easilysee that 0 will become very small as V, which represents the integerpart of the baseband signal, increases such that the real part becomesnegligible compared to the imaginary part. Therefore, equation (8) is avery good approximation for the large amplitude signals. For an EDGEsignal, the amplitude is always larger than certain amplitude in orderto keep its peak-to-minimum ratio of signal around 16.4 dB. V might belarge enough to satisfy the condition for equation (8) if the basebandinput signal is an EDGE signal. Validity of equation (8) for an EDGEsignal is verified by simulations and the results will be presentedlater. If equation (8) is valid, the same size of the amplitudepredistortion LUT as centered PWM can be employed for amplitudepredistortion of non-centered PWM. The LUT should be realized based onthe following equation:

$\begin{matrix}{{{{X_{H}({j\omega})}❘_{\omega = \frac{2\pi}{T}}} = {{{X_{NC}({j\omega})}❘_{\omega = \frac{2\pi}{T}}\frac{{- j}\;{vT}}{\pi}} = \frac{{- {{jsin}\left( \frac{\pi\; T}{T} \right)}}{\sin\left( \frac{\pi\; T}{T} \right)}T}{\pi}}}{v = {{\sin\left( \frac{\pi\; T}{T} \right)}{\sin\left( \frac{\pi\; T}{T} \right)}}}} & (9)\end{matrix}$Furthermore, FIG. 9-(c) indicates that not only an amplitudepredistortion LUT, but also a phase compensation LUT, should take theinteger part of the amplitude into account because the phase of thenon-centered PWM signal depends on the integer word as well as τ. As aresult, the size of the phase predistortion LUT will be huge. However,some approximation technique can help to reduce its size, too.

FIG. 10 shows a comparison 1000 of an ideal horizontal slicing signaland a non-centered PWM counterpart 1000. Note that the entire complexplane is rotated by 90° counterclockwise for easy tan⁻¹ approximation.The amount of phase distortion by non-centered PWM is θ, which is

$\begin{matrix}\begin{matrix}{\Theta = {\tan^{- 1}\left( \frac{\frac{{\cos\left( \frac{\prod\; T}{T} \right)}{\sin\left( \frac{\prod\; T}{T} \right)}T}{\prod}}{\frac{VT}{\prod} + \frac{{\sin\left( \frac{\prod T}{T} \right)}{\sin\left( \frac{\prod T}{T} \right)}T}{\prod}} \right)}} \\{= {\tan^{- 1}\left( \frac{{\cos\left( \frac{\prod T}{T} \right)}{\sin\left( \frac{\prod\; T}{T} \right)}}{V + {{\sin\left( \frac{\prod T}{T} \right)}{\sin\left( \frac{\prod T}{T} \right)}}} \right)}}\end{matrix} & (10)\end{matrix}$Thus, the amount of phase predistortion should be:

$\begin{matrix}\begin{matrix}{\phi = \theta} \\{= {- {\tan^{- 1}\left( \frac{{\cos\left( \frac{\prod T}{T} \right)}{\sin\left( \frac{\prod T}{T} \right)}}{V + {{\sin\left( \frac{\prod T}{T} \right)}{\sin\left( \frac{\prod T}{T} \right)}}} \right)}}}\end{matrix} & (11)\end{matrix}$where φ is the required phase predistortion for a non-centered PWMsignal. Approximation of tan⁻¹ by Taylor series is

$\begin{matrix}{{{\tan^{- 1}(x)} = {x - {\frac{1}{3}x^{3}} + {\frac{1}{5}x^{5}} - {\frac{1}{7}x^{7}\mspace{14mu}\ldots}}}{{\tan^{- 1}(x)} \approx {x\mspace{14mu}{if}\mspace{14mu} x\mspace{14mu}{is}\mspace{14mu}{close}\mspace{14mu}{to}\mspace{14mu}{{}_{}^{}{}_{}^{}}}}} & (12)\end{matrix}$Since θ converges to 0 if the integer part increases, as shown in FIG.10-(b), equation (12) is valid as far as the integer part is largeenough. With this approximation, equation (11) becomes a simpleclosed-form expression as follows:

$\begin{matrix}{{{\begin{matrix}{\phi = {- {\tan^{- 1}\left( \frac{{\cos\left( \frac{\prod T}{T} \right)}{\sin\left( \frac{\prod T}{T} \right)}}{V + {{\sin\left( \frac{\prod T}{T} \right)}{\sin\left( \frac{\prod T}{T} \right)}}} \right)}}} \\{\approx {- \frac{{\cos\left( \frac{\prod T}{T} \right)}{\sin\left( \frac{\prod T}{T} \right)}}{V + {{\sin\left( \frac{\prod T}{T} \right)}{\sin\left( \frac{\prod T}{T} \right)}}}}} \\{\approx {- \frac{{\cos\left( \frac{\prod T}{T} \right)}{\sin\left( \frac{\prod T}{T} \right)}}{V}}} \\{= {{{- \frac{1}{V}} \cdot {\cos\left( \frac{\prod T}{T} \right)}}{\sin\left( \frac{\prod T}{T} \right)}}}\end{matrix}{{if}\mspace{14mu} V}}\mspace{11mu} }\mspace{11mu}{\sin\left( \frac{\prod T}{T} \right)}{\sin\left( \frac{\prod T}{T} \right)}} & (13)\end{matrix}$Equation (13) implies that the phase predistortion LUT can be brokeninto two smaller LUTs and a multiplier. One LUT takes the integer wordof the amplitude signal and calculates

$\frac{1}{V}$while the other LUT takes the fractional word and calculates cos

$\left( \frac{\prod T}{T} \right){{\sin\left( \frac{\prod T}{T} \right)}.}$The total amount of the phase compensation is the multiplication ofthose two outputs. In this way, the phase predistortion LUT can beimplemented with less complexity. In a polar transmitter, the LUT tocompensate AM-PM distortion of RF PA is likely to already exist in thesystem. In this case, the LUT for

$\frac{1}{V}$can be combined with the existing AM-PM predistortion LUT, and only asmall LUT with the fractional word inputs calculating cos

$\left( \frac{\prod T}{T} \right){\sin\left( \frac{\prod T}{T} \right)}$and a multiplier are required additionally.

The validity of equation (13) is confirmed, as shown in FIG. 11. Theinteger word is 10 bits, which ranges from 0 to 1023, and the fractionalword is 5 bits (32 levels). The approximation in equation (13) agreeswell with equation (11) when the input code is over 100 although theydiffer when the input code is less than 6. Note that the input coderepresents the amplitude of an input baseband signal in a polartransmitter although we are currently dealing with phase compensationfor non-centered PWM. For an EDGE signal, the input code is alwayslarger than certain amplitude in order to keep its peak-to-minimum ratioas explained earlier. As a result, equation (13) is a very goodapproximation for EDGE, as verified by the later illustratedsimulations.

The resolution of the phase path of a polar transmitter is anotherrestriction to affect complexity of the entire system. The size of aphase predistortion LUT depends on not only the input resolution butalso the output resolution, which goes into the phase input of a PLL. Ifan ADPLL is employed, the resolution of the phase input of an ADPLL alsoaffects complexity of its building blocks, such as a DCO, a digital loopfilter, and a TDC. The required phase resolution of the non-centered PWMmethod can be determined by simulations, and the results with differentphase resolutions are presented later.

Note that the phase compensation 1200 for non-centered PWM should occurinstantly (i.e., having wide enough bandwidth) as illustrated in FIG.12. It means that an ADPLL should employ a special method such as atwo-point modulation. R. B. Staszewski et al. in ‘Just-in-time gainestimation of an RF digitally-controlled oscillator for digital directfrequency modulation’, published in IEEE Trans. Circuits Syst. II, vol.50, issue 11, pp. 887-892, November 2003 [10], which is incorporatedherein by reference, employs a feed-forward path for an instantphase/frequency shift, and also uses a predistortion path to compensateclosed-loop counteract; hence, the instant phase shift shown in FIG. 12is possible.

Amplitude Resolution Improvement Employing PWM

Given the previous analysis, the architecture for improving theamplitude resolution of a polar transmitter employing a PWM generatorwill be described. The architecture for centered and non-centered PWMshould differ because of their different characteristics. Firstly, wewill discuss the architecture for centered PWM, as disclosed in [6],with the architecture for non-centered then introduced. A simple delaychain circuit, which can be used in a PWM generator, will be alsodescribed and its circuit-level simulation results will be shown.Finally, centered and non-centered PWM methods will be compared.

Architecture Employing Centered PWM

Referring now to FIG. 13, an example of an architecture 1300 of a polartransmitter with a PWM generator, which creates centered PWM signals, isillustrated in accordance with some example embodiments of theinvention. Note that the architecture 1300 is augmented from theoriginal polar transmitter architecture depicted in FIG. 1. The buildingblocks drawn with the bold lines are added to the original polartransmitter to improve its amplitude resolution. In FIG. 13, the PWMgenerator 1302 generates 2^(N)PWM-level centered PWM signals. Theoriginal amplitude signal is N_(A)-bit. The integer part is N_(int)bits, and it drives the DPA's switching transistors directly. TheN_(frac)-bit signals, which is the fractional part of the amplitudesignal, go into the amplitude predistortion LUT 1304 for centered PWM,which is realized based on equation (4). The LUT 1304 has N_(frac)-bitinputs and N_(PWM)-bit outputs. It will occupy a very small area inmodern CMOS processes because its size is only 2^(N)frac words. In thisexample embodiment, we used a 5-bit fractional word as input and a12-level centered PWM signal as output, which are represented by 324-bit data words in the predistortion LUT 1304. Therefore, the size ofthe required LUT for centered PWM is: 2⁵-word×4-bit=128-bit. Note thatthis LUT can also be merged with the LUT for DPA in the original polartransmitter so as to minimize the area.

Referring now to FIG. 14, an example of a conceptual block diagram 1400of a centered PWM generator and its timing diagram are illustrated inaccordance with some example embodiments of the invention. In oneexample, two pulse signals, d₁ and d₂, are adjusted with two simpledelay chains 1402 and 1404 in order to produce the desired pulse output.

In order to achieve better centering ability, a Pulse Center block 1306,1406 in FIG. 13 and FIG. 14, which can be implemented with either a DLLor fine resolution delay lines, manipulates the main clock delay,thereby controlling the pulse position of the PWM signal. The PulseCenter block 1306/1406 plays an important role in that it keeps theposition of the PWM at the center of the first half cycle of the carriersignal as depicted in FIG. 4( b) across process variation. If the PWM isnot located at the center, it causes phase distortion of the outputsignal. Channel switching is another issue since pulse position isrelative to the clock period T. Therefore, the relative pulse positionchanges if the clock period is changed. The Pulse Center block 1306/1406can change the delay for the clock input of the PWM generator (clk₁)such that the pulse position is always centered no matter what TXchannel is selected.

Referring now to FIG. 15, an example of a polar transmitter 1500 withnon-centered PWM, is illustrated in accordance with some exampleembodiments of the invention. The novel architecture is augmented fromthe original polar transmitter architecture in FIG. 1. In FIG. 15, thePWM generator makes 2^(N)PWM-level non-centered PWM signals. The phaseLUT 1502 takes the N_(frac)-bit fractional word of the amplitude signalas an input, and it calculates cos

${\left( \frac{\prod T}{T} \right){\sin\left( \frac{\prod T}{T} \right)}},$as per equation (3). The N_(int)-bit integer word of the amplitudesignal goes to the building block 1504, which calculates the inverse. Itcould be an arithmetic logic or an LUT. In most commercial polartransmitter systems, there is an AM-PM LUT. Hence, the

$\frac{1}{in}$block 1504 can be simply combined with the existing LUT. The combinationof the phase LUT 1502 and the

$\frac{1}{in}$block 1504 calculates the approximated phase predistortion value asexplained earlier. The additional LUT 1506 for amplitude path is alsoused, and it takes the fractional word of the amplitude signal. Thecontent of the LUT 1506 is derived according to equation (9), which isan approximation. Note that the Pulse Center block is unnecessary inthis case because non-centered PWM is always aligned with the main clockas far as the PWM generator 1508 is referenced to the main clock.

Referring now to FIG. 16, an example of a conceptual block diagram 1600of a non-centered PWM generator and its timing diagram is illustrated,in accordance with some example embodiments of the invention. In thiscase, the generated PWM is aligned with the rising edge of the mainclock. If necessary, the building block in FIG. 16 can be easilymodified such that the PWM is aligned with the falling edge of the clockinstead of the rising edge. Then, the content of the amplitude and phasepredistortion LUTs should be changed, but the overall architecture willremain the same. Note that FIG. 16 requires only one delay chain 1602,as compared to the centered PWM generator shown in FIG. 14. Therefore,the architecture of FIG. 16 is much simpler overall to implement.

The PWM generators in FIG. 14 and FIG. 16 require a delay chain1402/1404/1602 where the delay is controllable digitally. A simpleinverter-based delay chain 1700 for the PWM generator is described inthis section. FIG. 17 illustrates the described circuit. The invertersinv₁, inv₂, inv₃, inv₄ are cascaded, and their input nodes can be set tothe desired logic levels by force in such a way that some inverters areheld to a certain voltage while the others propagate signals from theprevious stages. There are three possible states for each input node ofthe inverters inv₁-inv₄; high, low, and local floating. When the inputnode of the inverter inv₁/inv₂/inv₃/inv₄ is set to floating, the voltageof that node is determined by the previous stage; thus, that inverterinv₁/inv₂/inv₃/inv₄ propagates a digital signal. By controlling thenumber of the inverters propagating a signal, one can change the totalpropagation delay of the circuit.

FIG. 18 illustrates how the described circuit creates four inverterdelays 1800. In the reset state, the inputs of all four invertersinv₁-inv₄ are held at a certain voltage by pre-set devices at the inputnodes of the inverters inv₁-inv₄ such that the delay chain's output islow. In order to generate four inverter delays, the inputs of the lastthree inverters inv₂-inv₄ are set to floating. Now, the first stagedetermines the output. Therefore, after the input of the first inverterinv₁ goes to high, the signal propagates through the four inverters. Thetotal delay is:delay=t _(clk-to-start1)+4·delay_(inv)where: delay_(inv) is an inverter delay, and t_(clk-to-start1) is thetime to take for the input of inv_(i) to become high, which is the delayfrom the clock to the start of the signal. t_(clk-to-start1) isdetermined by the size of one of the pre-set devices, P₁, and the totalcapacitance of the input node of inv₁.

FIG. 19 illustrates the case of a three inverter delay 1900. In order tocreate three inverter delays, the inputs of the last two inverters inv₃and inv₄ become floating. When the input of the first two inverters inv₁and inv₂ are set to high and low, respectively, the signal propagatesthrough the last three inverters inv₂-inv₄ creating three inverterdelays. Note that the input of inv₁ is still low beforet_(clk-to-start1). Thus, inv₁ attempts to make the output, which is theinput of inv₂, high before t_(clk-to-start1) while N₂ tries to make theinput of inv₂ low. If N₂ is much larger than the size of inv₁, then theinput of inv₂ will become low by force even before t_(clk-to-start1). Inthis case, t_(clk-to-start2), the time to take for the input of inv₂ tobecome low, will be determined by the size of N₂ and the input nodecapacitance of inv₂. If the size of N₂ is small, then t_(clk-to-start2)will be longer than t_(clk-to-start1) because the input of inv₂ canbecome low only after the input of inv₁ becomes high. In any cases, thetotal delay of FIG. 19 is:delay=t _(clk-to-start2)+3·delay_(inv)Employing smaller inverters relative to the pre-set devices decreasesthe clock-to-start time, but increases the inverter delay. Thistrade-off should be taken into account for transistor sizing of thedescribed delay chain circuit.

The final propagation delay value of the described delay chain circuitis controlled by digital signals. Hence, the digital circuits thatgenerate the proper control signals for each stage are required.Moreover, those signals should be referenced to the clock in that theoutput of the delay chain should be a delayed clock. FIG. 20 depicts thedetails of the delay generator 2000 including the digital circuits tocreate the control signals for each stage. Note that AND and OR gateswith one input fed by the clock are required so that all the controlsignals are aligned with the clock. In addition, both clk and clk arerequired, as shown in FIG. 20. clk is usually available in PLLs using adifferential LC oscillator.

One drawback of the described circuit of FIG. 20 is that the loading forthe clock signal gets bigger and bigger as the number of inverter stagesincreases. However, the main clock is also supposed to drive a DPA,which is composed of 1024 equivalent unit switching transistors [1, 2].Compared to the clock loading by the switching transistors, theadditional loading caused by the delay stage is relatively small.Therefore, the additional clock loading will not require major designmodification of the conventional DPA circuits.

The post layout simulations of the described delay chain circuit aredone in a nanoscale CMOS process, such as 65 nm CMOS process. The totalnumber of inverter chains designed is 25, and the circuit simulationresults will be applied to the behavioural-level simulations of thedescribed system in the next section. Ideally, the delay created by thedescribed circuit is integer multiples of one inverter delay plus aclock-to-start time as explained earlier. However, the delay of eachinverter will be different because of device mismatch. The delayvariation of the inverters is estimated by Spectre Monte Carlosimulations. The estimated delay variation will also be taken intoaccount for the behavioural simulations of the described architecture inthe next section.

FIG. 21 illustrates a graphical example 2100 of a mismatch-averagedpropagation delay of the circuit 2000 of FIG. 20. FIG. 22 depicts themean delays and the standard deviations of the inverter stage. FIG. 22illustrates the incremental delay 2200 by each inverter stage, and thedelay of inv₂₅ includes the contribution of a clock-to-start time. Byenabling more inverters, the total propagation delay will increase insteps of around 19.5 psec., which is one inverter delay. However, theminimum propagation delay of the circuit is 35 psec. because the minimumdelay is one inverter delay plus a clock-to-start delay. The standarddeviation of each delay is less than 1 psec., which is about 5% of thenominal delay, and this result will be used for the behaviouralsimulations as described below.

FIG. 23 illustrates the mean delay of each inverter stage 2300 exceptfor inv₂₅, of which delay includes the clock-to-start delay. It showsthat the delay goes slightly up and down alternatively as the input codeincreases. This is because of the delay mismatch of rise and fall timesof the inverters.

Comparison of Centered and Non-Centered PWM

Centered and non-centered PWM show quite different characteristics asexplained above, so that they require different architectures. The PWMgenerators for each case also show different features in a practicalimplementation. Moreover, the resolution of each PWM generator isdifferent even if they have the same delay chains with the same unitdelay, assuming that the example PWM generators shown in FIG. 14 andFIG. 16 are employed.

Referring now to FIG. 24, a graphical example 2400 of a resolutioncomparison of centered and non-centered PWM generators with a unit delayof

$\frac{1}{8} \times \frac{T}{2}$(a) centered PWM (b) non-centered PWM is illustrated, in accordance withsome example embodiments of the invention. FIG. 24 explains the reasonfor the different PWM resolutions. The unit delay time is

$\frac{T}{16}.$The number of possible centered PWM signals is only ‘4’ because thepulse should be located at the center in all cases, but the number ofnon-centered PWM is ‘8’ as shown. Consequently, the time resolution ofnon-centered PWM is twice the time resolution of centered PWM.Theoretically, non-centered PWM can show better amplitude resolutionimprovement than centered PWM. However, it is worth mentioning that theamplitude resolution of non-centered PWM is also affected by theresolution of the phase path of the system, although the phaseresolution of a digital PLL is digitally controlled and it is typicallymade very fine without much burden. The amplitude resolution ofnon-centered PWM might also reduce for a certain baseband signal, suchas a signal with large peak-to-minimum ratio, unless the system employsthe full size LUTs for the amplitude and phase predistortion rather thanthe reduced size LUTs based on approximation. For an EDGE transmitteremploying an ADPLL, non-centered PWM could be the better choice sincethe baseband amplitude of an EDGE signal has a limited peak-to-minimumratio as mentioned before.

TABLE 5 Architectures with centered PWM vs. non-centered PWM centeredPWM non-centered PWM Amplitude LUT required required Size of 2^(N)^(frac) -word 2^(N) ^(int) ^(+N) ^(frac) -word (theory) amplitude LUT2^(N) ^(frac) -word (approximation) PWM generator 2 delay chains 1 delaychain circuit required required Resolution of PWM generator$\frac{T}{4 \cdot {delay}_{unit}} - {level}$$\frac{T}{2 \cdot {delay}_{unit}} - {level}$ Phase not required requiredcompensation Pulse Pulse position Pulse position positioning controlrequired control not requiredTable 5 summarizes the comparison of the described architectures withthe centered and non-centered PWM. There is a trade-off for PWM choicebetween the necessity of phase compensation and PWM generator'scomplexity. Obviously, a non-centered PWM generator is easier toimplement than a centered PWM generator, and it achieves better timeresolution than the centered PWM counterpart. However, non-centered PWMrequires phase compensation. Non-centered PWM would be the preferredchoice for a polar transmitter with an AM-PM predistortion LUT becausethe built-in phase predistortion LUT can be used for phase compensationof PWM signals as long as the resolution of the phase path is enough andthe PLL in a polar transmitter have the ability for instant phase shiftsuch as two-point modulation.Behavioural Simulations of the Example Architectures with the PWM Scheme

The effect of the described amplitude resolution improvement usingcentered and non-centered PWM is verified by a behavioural simulator,such as that described by M. Perrott in ‘CppSim behaviour simulatorpackage’ (available at http://www.cppsim.com) [10]. The simulation filesand the detailed description can be found in M. Park's publication‘Behavioural simulation of an amplitude resolution improvement for anRF-DAC employing PWM scheme’ (available athttp://www.cppsim.com/tutorials.html) [11]. The main objective of thedescribed architecture is to improve the amplitude resolution of a DPA.Thus, only the amplitude path is modeled in detail while the phase pathis modeled as ideal. The baseband input signal is the amplitudecomponent of an EDGE signal. The output spectrum will be compared withthat of the original DPA's behavioural model to show the improvement.

In the simulation model, the input to the DPA is 10 bits, but theamplitude signal of the baseband EDGE is ‘15’ bits. Thus, N_(int) is‘10’, and N_(frac) is ‘5’. The 5-bit fractional word controls thepulsewidth of the PWM signal. A 25-stage delay chain is modeled inCppSim, and the nominal delay of each stage is 20 ps, which is theworst-case delay of an inverter stage based on post-layout simulationsin 65 nm CMOS.

The non-linearity of a DPA is modeled based on the original 10-bit DPAcircuit. An amplitude predistortion LUT to linearize this nonlinearityis included in the simulation models given that the measurednonlinearity of the DPA is typically known from M. Perrot's ‘Fast andaccurate behavioural simulation of fractional-n frequency synthesizersand other PLL/DLL circuits’, Proc. 39^(th) Design Automation Conference,2002 pp. 498-503[12], which is incorporated herein by reference.

Delay mismatch effect of the delay chain is also included in thebehavioural simulations. Although the Spectre Monte Carlo simulationresults show about 5% of delay mismatch, we used 10% of delay mismatchfor the behavioural simulations to be on the conservative side.

Simulation Results with Centered PWM

The amplitude predistortion LUT for centered PWM is implemented based onthe simulated nominal delay of the delay elements, and its input data is5 bits because N_(frac) is 5. The carrier frequency in the simulation is1.0417 GHz, of which the period is 960 ps. Although this is not a legalGSM/EDGE frequency, we chose it merely for simulation convenience since960-ps is the integer multiple of the nominal delay of the delay stages,20-ps.

FIG. 25 shows the output spectrum 2500 of an original 10-bit DPA, and aDPA with centered PWM. It also compares the spectrum of the centered PWMwith and without the amplitude predistortion LUT. The quantization noiseof a DPA creates the noise skirt shown in FIG. 25. The quantizationnoise of the system employing 12-level PWM with the LUT is about 18 dBlower than that of the original 10-bit DPA, which means the amplituderesolution of the DPA improves by around 2.7 bits. However, thequantization noise of the centered PWM without the LUT is almost 10 dBworse than that of the PWM with the LUT.

Theoretically, the amplitude predistortion LUT for centered PWM can bebuilt based on the exact delay of each delay stage when delay mismatchexists. However, it is impractical since a precise method of measuringthe delay is required. In this example embodiment, we assume that theLUT for PWM is implemented based on the known nominal delay of the delayelements. In other words, the LUT is calibrated for only the processvariation, and does not take care of the delay mismatch. Therefore, anydelay mismatch, which is not compensated by the LUT, degrades theoverall performance. FIG. 26 shows the output spectrum 2600 showing that10% delay mismatch raises the quantization noise by up to 3 dB, whichleads to 2.2-bit resolution improvement over the original 10-bit DPA.Even with the 10% delay mismatch, the spectrum of the centered PWMmethod satisfies the 3GPP spectral mask for the associated RX band.

FIG. 27 depicts the output spectrum 2700 showing how much amplituderesolution is degraded when the position of PWM is not exactly at thecenter. Up to 6 dB more quantization noise is expected when the positionof the PWM signal is offset by 18 psec. In a practical implementation,the Pulse Center block 1306 in FIG. 13 will control the pulse positionproperly. Therefore, the pulse position error should not limit theperformance.

Simulation Results for Non-Centered PWM

FIG. 28 shows the output spectrum 2800 of an original 10-bit DPA and aDPA employing non-centered PWM with and without phase compensation. Thetime resolution of the non-centered PWM generator used in thesimulations is 20 ps, which is the nominal unit delay of the delay chaincircuit shown later. Delay mismatch is not considered. The amplitude andphase predistortion is done without the approximation technique, and thesize of each LUT is 2¹⁵ words in this case since the baseband input datais 15 bits as was in the simulations presented later. The quantizationnoise of the DPA with non-centered PWM is more than 20 dB lower thanthat of the original 10-bit DPA, which means the amplitude resolution isimproved by at least 3 bits. Due to the higher time resolution thancentered PWM, the amplitude resolution improvement is much better withnon-centered PWM, but requiring an overhead of LUTs. FIG. 28 alsoreveals that the quantization noise of the DPA with non-centered PWMbecomes much higher if it lacks phase compensation. Thus, phasecompensation is crucial for the non-centered PWM.

In the CppSim simulations, phase compensation is done by a variabledelay block. The simulation time step is 10 psec., but required timeresolution for phase compensation is much less than femto second for thesimulation in FIG. 28. Instead of decreasing the simulation time step,the signal discretization technique introduced in M. Perrot's ‘Fast andaccurate behavioural simulation of fractional-n frequency synthesizersand other PLL/DLL circuits’, Proc. 39^(th) Design Automation Conference,2002 pp 498-503 [13], which is incorporated herein by reference, isemployed for fast simulations.

FIG. 29 shows the output spectrum 2900 showing that the amplitudepredistortion with approximation for non-centered PWM, which isintroduced in equation (8), is adequate for an EDGE signal. Thedifference between the spectra for non-centered PWM with ideal amplitudeLUT and approximated amplitude LUT is less than ±0.2 dB. Therefore, thereduced-size amplitude LUT with approximation can be employed forsimpler implementation without resolution degradation.

FIG. 30 shows the output spectrum 3000 proving that the phasecompensation with approximation is also good enough for an EDGE signal.The spectra of the ideal and approximated phase compensation are almostthe same in FIG. 30, and the difference between the two spectra is lessthan ±0.4 dB. Accordingly, the architecture with reduced size LUTsdescribed in FIG. 15 is sufficient for an EDGE signal.

Even with the reduced-size amplitude and phase predistortion LUTs basedon approximation, non-centered PWM shows better resolution improvementthan centered PWM mainly because the time resolution of the non-centeredPWM generator is twice as much as that of the centered PWM, as pointedout in FIG. 24. In practice, however, the resolution of the phase pathin a digital PLL should be taken into consideration for the non-centeredPWM case. FIG. 31 shows the output spectra 3100 with different phaseresolutions. It is obvious that the quantization noise rises if thephase resolution is low. Compared with FIG. 26, FIG. 31 shows thatnon-centered PWM is worse than centered PWM if the resolution of thephase path is lower than 0.05° even with the twice time resolution ofthe PWM generator. Therefore, the phase resolution of a PLL is anotherdesign constraint for non-centered PWM, in general. Note that thetypical phase resolution in ADPLL is 1.5 Hz, which will make about 10000times better resolution than 0.005° at 1 GHz of carrier frequency. Thus,the phase resolution is not an issue.

The Spectre Monte Carlo simulation results illustrated later are appliedto the behavioural simulations to see the mismatch effect on thespectrum. 10% of standard deviation is used for the behaviouralsimulations.

FIG. 32 shows an example of the output spectrum 3200 for non-centeredPWM with 10% delay mismatch. The phase resolution is 0.005° in thesimulations. The amplitude and phase LUT are realized based onapproximation to reduce the size of the LUTs. Delay mismatch increasesthe quantization noise level by around 3 dB. In other words, delaymismatch lowers the resolution by around 0.5 bits. Therefore, theamplitude resolution improves by about 2.5 bits if non-centered PWM isemployed with 10% delay mismatch.

Referring now to FIG. 33, a block diagram of a wireless communicationunit (sometimes referred to as a mobile subscriber unit (MS) in thecontext of cellular communications or a user equipment (UE) in terms ofa 3^(rd) generation partnership project (3GPP™) communication system) isshown, in accordance with some embodiments of the invention. Thewireless communication unit 3300 contains an antenna 3302 preferablycoupled to a duplex filter or antenna switch 3304 that providesisolation between receive and transmit chains within the MS 3300.

For completeness, the receiver chain, as known in the art, includesreceiver front-end circuitry 3306 (effectively providing reception,filtering and intermediate or base-band frequency conversion). Thefront-end circuitry 3306 is serially coupled to a signal processingfunction 3308. An output from the signal processing function 3308 isprovided to a suitable output device 3310, such as a speaker, screen orflat panel display. A controller 3314 maintains overall subscriber unitcontrol and is coupled to the receiver front-end circuitry 3306 and thesignal processing function 3308 (generally realised by a digital signalprocessor (DSP) 3330). The controller 3314 is also coupled to a memorydevice 3316 that selectively stores operating regimes, such asdecoding/encoding functions, synchronisation patterns, code sequences,RSSI data and the like.

In accordance with examples of the invention, the memory device 3316 maycomprise the aforementioned LUT.

As regards the transmit chain, this essentially includes an input device3320, such as a microphone or a keypad, coupled to the signal processingmodule 3308 and thereafter direct to a digitally controlled poweramplifier (DPA) 3324 and to the antenna 3302. The DPA 3324 isoperationally responsive to the controller 3314 that, in one exampleembodiment comprises, or is operably coupled to, a PWM generatorarranged to generate a dynamically incremental PWM signal.

The signal processor function 3308 in the transmit chain may beimplemented as distinct from the processor in the receive chain.Alternatively, a single processing function 3308 may be used toimplement processing of both transmit and receive signals, as shown inFIG. 33. Clearly, the various components within the wirelesscommunication unit 3300 can be realised in discrete or integratedcomponent form, with an ultimate structure therefore being merely anapplication-specific or design selection.

FIG. 34 illustrates an example of a RF-DAC 3400 employing PWM, accordingto example embodiments of the invention. The RF-DAC 3400 is operablycoupled to a digitally controlled oscillator (DCO) 3425 (which in thisexample and in a number of further examples will not formally be part ofthe RF-DAC and may be configured to provide an input to an RF-DAC IC)that receives a tuning word input signal 3420, which in this example iszero-order hold (ZOH) at a sampling rate ranging from FREF to 100's ofMHz. The DCO 3425 has an output of a pulse width of ˜500 psec based on aplurality of codes that provides the primary input to the RF-DAC 3400.The output 3430 from the DCO 3425 is input to a first ‘AND’ logic module3445 of an integer DPA 3435 where it is ‘AND’ed with an amplitudecontrol word (ACW) signal. The output from the first ‘AND’ logic module3445 is input to the integer part of the power generation stage, whichin this example is in a form of a switch transistor 3450 foramplification. The output 3455 of the switch transistor 3450 is input toa matching network 3460 and a matched output signal 3495 produced.

The dynamically incremental PWM signal is generated using a pulseslimmer circuit 3465 and a fractional DPA 3490 comprising one or moretransistors for use with the one or more LSBs. The pulse slimmer circuit3465 comprises a DTC 3475 arranged to receive the output 3430 from theDCO 3425 and controlled by a delay control signal 3470. The output 3480from the DTC 3475, together with the output 3430 from the DCO 3425 isinput to a second ‘AND’ logic module 3485, which is input to thetransistor of the fractional DPA 3490. The output of the fractional DPA3490 controls the output of the switch transistor 3450 by injecting awell-controlled delta energy into the matching network 3460. A graphicalrepresentation of the signal at the DPA output node ‘X’ 3455, i.e.before the matching network 3460, is illustrated. The graphicalrepresentation of the signal at the DPA output node ‘X’ 3455 illustratesthe summation of the regular MOS switch 3450 in the integer DPA 3435 andone switch in the fractional DPA 3490 that undergoes incremental PWM(iPWM). In this manner, the PWM signal is applied only on the LSB bit(s)(and LSB transistor(s)).

FIG. 35 illustrates timing waveforms 3500 of the example RF-DACemploying PWM of FIG. 34 according to example embodiments of theinvention. The timing waveforms 3500 comprise a clock signal (CKV) 3505,a delayed clock signal (CKV_DLY) 3515, and the PS_Out signal 3520 fromthe second ‘AND’ logic module 3485, which controls the switching on ofthe transistor of the fractional DPA 3490.

The duty cycle of the PS_Out signal from the second ‘AND’ logic module3485 is shown in graph 3525, with the duty cycle varying 3530 between 0%and 50%. A delay of the edges of the PS_Out signal 3520 with respect tothe CKV clock signal 3505 is illustrated in waveforms 3540, where eachstep contributes about 20 psec/500 psec to the LSB step. Thus, byturning on additional inverters, the timing resolution can be configuredto be approximately 20 psec. The pulse width of the 1 GHz clock is 500ps, so 20 psec/500 ps is the relative resolution or granularity.

FIG. 36 illustrates an example of a delay cell design 3600, adapted toemploy example embodiments of the invention, which can be employed toproduce the delay control signal 3480 of FIG. 34. The delay cell design3600 in this example comprises a plurality of serially coupled r-scircuits 3640, which may be implemented as shown in circuit 3610. Theset (s) port of the plurality of serially coupled r-s flip flops 3640are each fed from a plurality of respective ‘AND’ logic modules 3630.The inputs of the respective ‘AND’ logic modules 3630 are fed from theclock (CLK) source 3625 and data bits d[0]-d[n]. In this manner, theclock signal delay output from the delay cell design 3600 can bedynamically controlled via the data bits d[0]-d[n], which can bedetermined based on values stored in the LUT.

FIG. 37 illustrates two different example quantization methods foradding an extra 3-bit resolution in either a voltage or current signalof the example RF-DAC employing PWM of FIG. 34 and thereby improving anamplitude resolution of the RF-DAC according to example embodiments ofthe invention. A first example quantization method uses horizontalslicing 3700, and a second example quantization method uses verticalslicing 3725. For the DPA, the vertical axis 3705 represents the currentor the conductance of the switching transistors, which is directlyproportional to the output envelope.

In the first example quantization method using horizontal slicing 3700,which is a conventional quantization method for a DAC, the originalresolution is 10 bits in the system 10-bit quantization 3710 with anadditional 3-bit quantization resolution 3715 provided using horizontalslicing to achieve the ideal 13-bit signal (i.e. a 10-bit quantization3710 plus an additional 3-bit quantization 3715) that would typically berequired to meet the EDGE noise specification. For the horizontalslicing scheme, the resolution is set by the available area and power ofswitching transistors along with device mismatch which limits theminimum device size.

The second example quantization method uses vertical slicing 3725 of asignal, where the output amplitude is controlled by a time interval ofthe vertically sliced signal. Thus, this quantization method isPWM-based, whose pulsewidth has a limited number of quantizedpulsewidths. The original resolution is 10 bits in the system 10-bitquantization 3735 with an additional 3-bit quantization resolution 3740provided using vertical slicing to achieve the ideal 13-bit signal (i.e.a 10-bit quantization 3735 plus an additional 3-bit quantization 3740)that would typically be required to meet the EDGE noise specification.The resolution of the vertical slicing scheme is set by time-resolution.Accordingly, the vertical slicing scheme is able to achieve higherresolution than the horizontal slicing with the same minimum device sizeif time-resolution is higher. In modern nanometer-scale CMOS technology,time-resolution is becoming higher. Thus, employing PWM is better choiceto improve the amplitude resolution of a DPA.

FIG. 38 illustrates graphically a comparison 3800 of the twoquantization methods to achieve the 3-bit quantization in thebit-quantization example employing PWM of FIG. 34 and FIG. 37 accordingto example embodiments of the invention. Thus, a first graphical exampleillustrates a fractional portion of horizontal slicing 3805. A secondgraphical example illustrates a fractional portion of vertical slicing3825. On the time axis 3820, 3835, T is the time period of an RF carriersignal. In the first graphical example of horizontal slicing 3805, the ⅜y-axis point 3810 is a voltage/current level generated by the unitswitching device. In the second graphical example of vertical slicing3825 (T/2*3/8) is a pulsewidth 3840 for vertical slicing. Note that theamplitude switches are only turned on during half the DCO period, i.e.T/2. The full size of the voltage/current level generated by the unitswitching device is illustrated as being normalized to ‘1’. In thisexample, the fractional word adds an extra 3-bit resolution with,therefore, ‘8’ extra amplitude levels. The pulse position of the PWMsignal is assumed to be at the center of the first half cycle of thecarrier signal in this case. Intuitively, both signals from FIG. 38 arethe same in terms of power, because the total area of the signals is thesame. As pointed out above, however, they are equivalent only at DC3850. Notably, FIG. 38 clearly illustrates that the horizontal andvertical slicing is not the same at the carrier frequency which is 1/THz. An RF-DAC is intended to generate a signal at a carrier frequencycorresponding to an input digital code. Therefore, the vertical slicingsignal in FIG. 37 and FIG. 38 creates an incorrect RF signal even thoughit creates an accurate DC signal. An inaccurate RF signal from an RF-DACleads to higher quantization noise.

FIG. 39 illustrates a bit-quantization example 3900 using digitalpre-distortion for selecting a PWM pulse width of FIG. 38 according toexample embodiments of the invention. Here, a 3-bit quantization process3920 is used, providing 8 respective pulse widths 3935, 3940 to beapplied to the PWM signal. Each of the 3-bit quantization levels 3925correspond 3930 to a respective pulse width 3935, 3940.

Referring now to FIG. 40, a flowchart 4000 of an operation of a RF-DACemploying iPWM is illustrated according to example embodiments of theinvention. The flowchart starts at step 4010 and moves on to step 4020where an input signal, for example an amplitude sample, is received bythe IC and is to be transmitted at a particular time index or point intime. The amplitude sample is then divided into constituent integer andfractional parts, as shown in step 4030. The integer part is then outputto the integer part of the RF-DAC in step 4040 and the fractional partoutput to the PWM modulator in step 4050. In accordance with the contentof the integer part and the fractional part, the RF duty cycle per PWMmodulator output is either narrowed or broadened to obtain anincremental or decremental PWM signal, as shown in step 4060. Theinteger part of the RF-DAC output and the narrowed or broadened RF dutycycle are then combined in step 4070 to produce an output signal. Adetermination is then made as to whether the transmission has ended instep 4080, and if not the process advances to the next time index ortime point in step 4090 and loops back to step 4020. If the transmissionhas completed in step 4080, the process ends in step 4085.

Thus, example embodiments of the invention have described a newarchitecture for amplitude resolution improvement of an RF-DAC usingtime as the key signal domain. The technique employs incremental PWMachieved with a fine precision of an inverter delay. Since it exploitsthe fine timing resolution of nanometer-scale CMOS technology, it doesnot require tighter device matching.

Furthermore, example embodiments of the invention have categorized PWMinto centered and non-centered PWM, and showed that they have differentcharacteristics. The transmitter structures for both centered andnon-centered PWM is described. They are compared in the context of theperformance and implementation methods. Detailed behavioural simulationsshow that the architecture employing non-centered PWM is better thanthat of centered PWM. The simulations with non-centered PWM show about2.5-bit resolution improvement in a 1-GHz RF-DAC generating the EDGEenvelope, assuming 20-psec. time granularity of delay chains andincluding 10% delay mismatch. The described architecture can simplyaugment a digitally-intensive polar transmitter without majorarchitectural modifications. The building blocks required for thedescribed architectures are a PWM generator, a fine-resolution delaycontroller, and amplitude/phase predistortion LUTs for PWM signals.

Although some aspects of the invention have been described withreference to their applicability to an EDGE implementation of an UMTS™(Universal Mobile Telecommunication System) cellular communicationsystem and in particular to a UMTS™ wireless communication unit of a3^(rd) generation partnership project (3GPP) system, it will beappreciated that the invention is not limited to this particularcellular communication system. It is envisaged that the conceptdescribed above may be applied to any other cellular communicationsystem.

Example embodiments of the invention have determined that an incrementalPWM of DPA approach may offer improved performance over the traditionalΣΔ noise shaping approach. Example embodiments of the invention maybenefit from a reduced phase noise using an incremental PWM approach asthe PWM generated signal undergoes a division of 30 dB (i.e., 10*log10(1024)—noise power) reduction. Example embodiments of the inventionmay benefit from a use of a single inverter noise contribution, whichwould typically add 2 nV/sqrt(Hz).

Example embodiments of the invention may benefit from only applying theincremental PWM signal to the one or more least significant bit (LSB)transistor(s).

Example embodiments of the invention may benefit from preserving a maindigitally controlled power amplifier structure and coupling theincremental PWM circuit or module thereto.

Example embodiments of the invention may benefit from starting with alower quantization level and may benefit from requiring a lower clockrate. Example embodiments of the invention using an incremental PWMapproach may benefit from a 15 psec delay in the time domain, whichcorresponds to >14 bits of amplitude resolution.

Example embodiments of the invention may be achieved using much lowersilicon area and power than known techniques. Example embodiments of theinvention may benefit from superior re-programmability. Exampleembodiments of the invention may benefit from being suitable formulti-radio or multi-mode or multi-standard systems.

Example embodiments of the invention may also add inverter stages inparallel, for example in situations or applications where there may belimited range.

In particular, it is envisaged that the aforementioned inventive conceptcan be applied by a semiconductor manufacturer to any integrated circuitcomprising a digitally controlled power generation stage, for example ina form of a switch transistor, for example those of the MediaTek™ RF-SoCfamily of wireless products. It is further envisaged that, for example,a semiconductor manufacturer may employ the inventive concept in adesign of a stand-alone device, such as a silicon-on-chip (SoC) device,or application-specific integrated circuit (ASIC), any other sub-systemelement and/or discrete hardware/firmware/software components.

It will be appreciated that, for clarity purposes, the above descriptionhas described embodiments of the invention with reference to differentfunctional units and processors. However, it will be apparent that anysuitable distribution of functionality between different functionalunits or processors, for example with respect to the beamforming moduleor beam scanning module, may be used without detracting from theinvention. For example, functionality illustrated to be performed byseparate processors or controllers may be performed by the sameprocessor or controller. Hence, references to specific functional unitsare only to be seen as references to suitable means for providing thedescribed functionality, rather than indicative of a strict logical orphysical structure or organization.

Aspects of the invention may be implemented in any suitable formincluding hardware, software, firmware or any combination of these. Theinvention may optionally be implemented, at least partly, as computersoftware running on one or more data processors and/or digital signalprocessors or configurable module components such as FPGA devices. Thus,the elements and components of an embodiment of the invention may bephysically, functionally and logically implemented in any suitable way.Indeed, the functionality may be implemented in a single unit, in aplurality of units or as part of other functional units.

Although the present invention has been described in connection withsome embodiments, it is not intended to be limited to the specific formset forth herein. Rather, the scope of the present invention is limitedonly by the accompanying claims. Additionally, although a feature mayappear to be described in connection with particular embodiments, oneskilled in the art would recognize that various features of thedescribed embodiments may be combined in accordance with the invention.In the claims, the term ‘comprising’ does not exclude the presence ofother elements or steps.

Furthermore, although individually listed, a plurality of means,elements or method steps may be implemented by, for example, a singleunit or processor. Additionally, although individual features may beincluded in different claims, these may possibly be advantageouslycombined, and the inclusion in different claims does not imply that acombination of features is not feasible and/or advantageous. Also, theinclusion of a feature in one category of claims does not imply alimitation to this category, but rather indicates that the feature isequally applicable to other claim categories, as appropriate.

Furthermore, the order of features in the claims does not imply anyspecific order in which the features must be performed and in particularthe order of individual steps in a method claim does not imply that thesteps must be performed in this order. Rather, the steps may beperformed in any suitable order. In addition, singular references do notexclude a plurality. Thus, references to ‘a’, ‘an’, ‘first’, ‘second’,etc. do not preclude a plurality.

Thus, an improved amplitude resolution of an RF-DAC IC and methodtherefor have been described, wherein the aforementioned disadvantageswith prior art arrangements have been substantially alleviated.

LIST OF REFERENCES

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What is claimed is:
 1. An integrated circuit comprising: adigitally-controlled power generation stage for converting an inputsignal to a radio frequency (RF) carrier, the digitally-controlled powergeneration stage comprising a plurality of selectable switching devicescapable of adjusting an envelope of the RF carrier; and a pulse widthmodulator (PWM) generator arranged to generate a PWM control signalaccording to a fractional word of an amplitude signal and operablycoupleable to the plurality of selectable switching devices of thedigitally-controlled power generation stage; wherein the PWM generatorinputs the PWM control signal to a subset of the plurality of theselectable switching devices such that a PWM signal adjusts the envelopeof the RF carrier output from the digitally-controlled power generationstage.
 2. The integrated circuit of claim 1 wherein the integratedcircuit comprises a radio-frequency digital-to-amplitude converter(RF-DAC) comprising the digitally-controlled power generation stage,wherein the RF-DAC comprises at least one clock input for receiving adigital carrier signal and at least one data input for receiving aninput digital envelope signal.
 3. The integrated circuit of claim 1wherein the plurality of selectable switching devices comprises an arrayof digitally-controlled switches coupled to both a first clock input anda first data input, wherein a first portion of the array ofdigitally-controlled switches is arranged to generate the envelope ofthe RF carrier output from the digitally-controlled power generationstage with an amplitude substantially proportional to a signal at thefirst data input and wherein a second portion of the array ofdigitally-controlled switches is arranged to generate an additive RFsignal to be added to the envelope of the RF carrier via the PWM signal.4. The integrated circuit of claim 1 wherein the PWM generator comprisesa delay controller arranged to control a delay of the PWM control signalthat controls the PWM signal adjusting the envelope RF carrier outputfrom the digitally-controlled power generation stage.
 5. The integratedcircuit of claim 1 wherein the PWM generator comprises a plurality ofinverters, a number of which are dynamically selected to set a pulsewidth of the PWM control signal provided to the subset of the pluralityof selectable switching devices such that the PWM signal adjusts theenvelope output RF carrier output from the digitally-controlled powergeneration stage.
 6. The integrated circuit of claim 1 wherein the PWMsignal is added to the envelope RF carrier output from thedigitally-controlled power generation stage to control a signal timingof the digitally-controlled power generation stage.
 7. The integratedcircuit of claim 1 wherein the PWM generator provides the PWM controlsignal to the subset of the plurality of the selectable switchingdevices such that either a centered PWM signal or a non-centered PWMsignal adjusts the envelope RF carrier output from thedigitally-controlled power generation stage dependent upon a relativepulse position of the input signal to the digitally-controlled powergeneration stage.
 8. The integrated circuit of claim 7 furthercomprising a pulse center module arranged to adjust a delay of a mainclock signal employed by the integrated circuit to control the relativepulse position of the centered PWM signal.
 9. The integrated circuit ofclaim 1 further comprising a memory operably coupleable to the PWMgenerator and arranged to store a plurality of amplitude and/or phaseparameters associated with dynamically generating a non-centered PWMsignal.
 10. The integrated circuit of claim 9 wherein the memory isarranged to store a plurality of amplitude and/or phase predistortionparameters associated with the PWM control signal, such that the PWMsignal is predistorted based on at least one of the plurality ofamplitude and/or phase predistortion parameters.
 11. The integratedcircuit of claim 7 wherein the PWM generator is arranged to generate adynamically non-centered incremental PWM signal when a basebandamplitude of a phase-modulated RF carrier has a limited peak-to-minimumratio.
 12. The integrated circuit of claim 1 wherein the subset ofswitching devices is/are activated for a limited period of time within aradio frequency burst of a digitally-controlled power generation stagetransmission.
 13. The integrated circuit of claim 12 wherein the subsetof switching devices is/are activated during a positive half-cycle of aRF period within the radio frequency burst of the digitally-controlledpower generation stage transmission.
 14. The integrated circuit of claim9 further comprising a multiplier operably coupled to the memory thatcomprises at least two sub-memory elements, such that a first memory isresponsive to an integer word of the amplitude signal to be applied tothe digitally-controlled power generation stage to produce a first$\left( \frac{1}{V} \right)$ output and a second memory is responsive tothe fractional word to produce a second$\left( {{\cos\left( \frac{\pi\; T}{T} \right)}{\sin\left( \frac{\pi\; T}{T} \right)}} \right)$output such that a phase compensation to be applied in generating thenon-centered PWM signal is a multiplication of the first and secondmemory outputs.
 15. The integrated circuit of claim 9 wherein the memoryis additionally arranged to store polar co-ordinate data associated withthe digitally-controlled power generation stage.
 16. The integratedcircuit of claim 1 wherein the digitally-controlled power generationstage is capable of controlling an envelope of a phase-modulated RFcarrier.
 17. A method of controlling an envelope of a radio frequency(RF) carrier output from a digitally-controlled power generation stagecomprising a plurality of selectable switching devices, the methodcomprising: generating a pulse width modulator (PWM) control signalaccording to a fractional word of an amplitude signal; selecting asubset of the plurality of selectable switching devices to receive thePWM control signal; and, in response thereto generating a PWM signal toadjust the envelope of the RF carrier output from thedigitally-controlled power generation stage.
 18. The method of claim 17further comprising receiving an input signal to be transmitted, whereinthe input signal is split into an integer part and a fractional part.19. The method of claim 18 further comprising inputting the fractionalpart to a PWM generator to produce the PWM control signal in responsethereto.
 20. The method of claim 18 wherein adjusting the envelope RFcarrier output from the digitally-controlled power generation stagecomprises adding the integer part of the input signal to the generatedPWM signal.
 21. The method of claim 17 wherein generating the PWM signalto adjust the envelope RF carrier output from the digitally-controlledpower generation stage comprises adjusting a RF duty cycle of the PWMcontrol signal.
 22. A wireless communication unit comprising: adigitally-controlled power generation stage for converting an inputsignal to a radio frequency (RF) carrier, the digitally-controlled powergeneration stage comprising a plurality of selectable switching devicescapable of adjusting an envelope of the RF carrier; and a pulse widthmodulator (PWM) generator arranged to generate a PWM control signalaccording to a fractional word of an amplitude signal and operablycoupleable to the plurality of selectable switching devices of thedigitally-controlled power generation stage; wherein the PWM generatorinputs the PWM control signal to a subset of the plurality of theselectable switching devices such that a PWM signal adjusts the envelopeof the RF carrier output from the digitally-controlled power generationstage.